Education

University of Massachusetts at Amherst

• 1996, Ph.D. - Dissertation: "Low-Power Techniques for Global Communication in CMOS VLSI"
• 1994, M.S. in Electrical and Computer Engineering

"Politehnica" University, Bucharest, Romania

• 1984, Diploma in Electronics and Communications - Thesis: "Fermat and Mersenne Number Theoretic Transforms on a Bit-Slice Architecture".

Professional Employment History

University of Virginia, Charlottesville, VA

• 2008 - present, Professor in the Charles L. Brown Department of Electrical and Computer Engineering
• 2002 - 2008, Associate Professor in the Charles L. Brown Department of Electrical and Computer Engineering
• 1996 - 2002, Assistant Professor in the Charles L. Brown Department of Electrical and Computer Engineering. Head of the High-Performance Low-Power (HPLP) VLSI laboratory. Research in low-power and high-performance VLSI, temperature-aware design, digital and mixed-signal circuits, embedded systems, and nanoelectronics. Teaching ECE 736 - Advanced VLSI Design ( Spring 2002, Fall 1999, Spring 1997). ECE 687 - Physically-Aware Design ( Spring 2006). ECE 686 - SOC Design ( Fall 2006, Fall 2002). ECE 563 - Introduction to VLSI Design ( Fall 2005, Fall 2003, Spring 2003, Fall 2001, Fall 2000, Fall 1999, Fall 1998, Fall 1997, Fall 1996). ECE 436 - Advanced Digital Design ( Spring 2007, Spring 2006, Spring 2000, Spring 1999, Spring 1998). ECE 408 - Bluetooth CSIDC project ( Spring 2002, Spring 2001). ECE 363 - Digital Integrated Circuits ( Spring 2001). ECE/CS 230 - Digital Logic Design ( Fall 2007, Spring 2004). ECE 203 - Introduction to Circuits ( Fall 2002, Fall 2001).

University of California, Berkeley, CA

• 2004-2005, Visiting Faculty in the Berkeley Wireless Research Center (BWRC)

Intel Corp., Portland, OR

• 2002 summer, 1999 summer, Visiting Faculty in the Circuit Research Lab (CRL) of the Intel Microprocessor Technology Lab (MTL) (former Microprocessor Research Lab - MRL). Developed high performance, low power circuit design techniques.

IBM, Essex Junction, VT

• 2000 summer, Visiting Faculty in the ASIC Microelectronics Division of IBM. Developed low power circuits methodology for ASICs
.

University of Massachusetts, Amherst, MA

• 1991 - 1996, Graduate Research and Teaching Assistant in the Electrical and Computer Engineering Department. Research in low-power VLSI, robot-path planning, analog and mixed-signal circuits.

Atis-Uher, Ltd., Atlanta, GA

• 1993 and 1995, Senior Systems Engineer. Engineered for production a professional digital voice recorder (DVR) based on an embedded PC with a custom parallel signal acquisition architecture. Developed a novel group code recording (GCR) with low-DC component for digital recording and engineered for production a SCSI VHS-based digital recorder developed in cooperation with JVC, Japan.

Graphica Computer Corp., Tokyo, Japan

• 1991, R&D Engineer. Developed a SCSI-based RAID 3 embedded architecture for high-throughput applications in computer graphics using standard, off-the-shelf, hard drives in a parallel configuration. This RAID 3 approach was used in all systems subsequently developed at Graphica.

ITC - Research Institute for Computers, Bucharest, Romania

• 1984 - 1990, R&D Engineer. Contributed to the architecture definition for the I-106 minicomputer family, especially the I/O system design. Developed several embedded controllers for disk and tape drives.

Descriptive Biography

Mircea R. Stan received the Ph.D. (1996) and M.S. (1994) degrees in Electrical and Computer Engineering from the University of Massachusetts at Amherst and the Diploma (1984) in Electronics and Communications from "Politehnica" University in Bucharest, Romania. Since 1996 he has been with the Department of Electrical and Computer Engineering at the University of Virginia, where he is now a professor. Prof. Stan is teaching and doing research in the areas of high-performance low-power VLSI, temperature-aware circuits and architecture, embedded systems, and nanoelectronics. He has more than eight years of industrial experience, has been a visiting faculty at UC Berkeley in 2004-2005, at IBM in 2000, and at Intel in 2002 and 1999. He has received the NSF CAREER award in 1997 and was a co-author on best paper awards at ISQED 2008, GLSVLSI 2006, ISCA 2003 and SHAMAN 2002. He was the chair of the VLSI Systems and Applications Technical Committee (VSA-TC) of IEEE CAS in 2005-2007, general chair for ISLPED 2006 and for GLSVLSI 2004, technical program chair for NanoNets 2007 and ISLPED 2005, and on technical committees for numerous conferences. He has been an Associate Editor for the IEEE Transactions on Circuits and Systems Systems I in 2004-2008 and for the IEEE Transactions on VLSI Systems in 2001-2003. He has also been a Guest Editor for the IEEE Computer special issue on Power-Aware Computing in December 2003 and a Distinguished Lecturer for the IEEE Solid-State Circuits Society (SSCS) in 2007-2008, and for the IEEE Circuits and Systems (CAS) Society for 2004-2005. Prof. Stan is a senior member of the IEEE, a member of ACM, IET (former IEE), Usenix, and also of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi.

Informal Biography

I've been in the ECE department at the University of Virginia since 1996, right after getting my PhD from UMass Amherst. In a previous life, before my graduate studies, I worked for 8 years as an R&D Engineer designing peripheral controllers for minicomputers (anyone remember those PDP's and VAX's from DEC?). My professional/academic interests are still in the computer hardware area, but mostly at the circuits/VLSI level and more recently at the nanoscale. I have been periodically visiting companies such as Intel and IBM over the summer to keep me on my toes professionally and I've spent the 2004-2005 accademic year on sabbatical in the Berkeley Wireless Research Center at UC Berkeley.
In my spare time (what?) I like skiing, hiking and camping with my family of 2+3 (a boy and two girls, in a curious turn of events our kids have been born within a span of 9 days at the begining of October, but with long gaps in between, 6 years between the first and the second, 8 years between the second and the third).

Honors and Awards

• IEEE Solid-State Circuits Society (SSCS) Distinguished Lecturer, 2007-2008.
• 2007, Technical Program chair of NanoNets 2007 symposium.
• Best student paper award with Lloyd Harriott, John Bean, James Tour, and students at the Great Lakes Symposium on VLSI (GLSVLSI), for the paper "Design Approaches for Hybrid CMOS/Molecular Memory based on Experimental Device Data", Philadelphia, PA, May 2006.
• 2006, Second prize winner with a student team in the second (final) phase of the "SOC Design Challenge" contest organized by the SRC.
• 2006, General chair of ISLPED 2006 symposium.
• 2005, First prize winner with a student team in the first phase of the "SOC Design Challenge" contest organized by the SRC.
• IEEE Circuits and Systems (CAS) Society Distinguished Lecturer, 2004-2005.
• 2005, Technical Program chair of ISLPED 2005 symposium.
• Associate editor for the IEEE Transactions on Circuits and Systems I, 2004-present.
• 2004, Finalist and Honorable Mention with prof. Ron Williams and a student team in the "Computer Society International Design Competition (CSIDC)" organized by the IEEE Computer Society.
• Selected as a 2003 IEEE Micro Top Picks significant paper of the year in computer architecture with K. Skadron and students for the paper "Temperature-aware computer systems: opportunities and challenges" IEEE Micro, vol. 23, issue 6, pp. 52-61, Nov.-Dec. 2003
• Best paper award with Kevin Skadron and students at the International Symposium on Computer Architecture (ISCA) for the paper "Temperature-Aware Microarchitecture", San Diego, CA, June 2003.
• 2003, Finalist and Honorable Mention with two student teams in the "SiGe Design Challenge" contest organized by the Semiconductor Research Corporation (SRC).
• 2003, General chair of GLSVLSI 2003 symposium.
• 2003, membership in the Eta Kappa Nu honor society.
• 2002, Finalist and Fourth Place Winner with prof. Ron Williams and a student team in the "Computer Society International Design Competition (CSIDC)" organized by the IEEE Computer Society.
• Best student paper award with John Lach, Kevin Skadron, Marty Humphrey and students at the Workshop on Self-Healing, Adaptive and self-MANaged Systems (SHAMAN), held in conjunction with the ACM International Conference on Supercomputing, for the paper "Control-Theoretic Dynamic Frequency and Voltage Scaling", New York, NY, June 2002.
• 2002, University of Virginia Teaching Fellow.
• 2001, associate editor for the IEEE Transactions on VLSI Systems.
• 2001, Finalist and Honorable Mention with prof. Ron Williams and a student team in the "Computer Society International Design Competition (CSIDC)" organized by the IEEE Computer Society.
• 2000, Finalist and Honorable Mention with a student team in the "Cu Design Challenge" contest organized by the Semiconductor Research Corporation (SRC).
• 1998, Senior member of the IEEE.
• 1997, NSF CAREER award for "Advances in Theory, Design Methods, and CAD for Low-Power VLSI".
• 1997, voted best project by the University SIG of the Mentor Users Group for "Schematic Driven Layout for Analog VLSI Design".
• 1997, life member of Phi Kappa Phi honor society.
• 1995/1996, Outstanding Teaching Assistant Award, University of Massachusetts at Amherst.
• 1996, membership in the Phi Kappa Phi honor society.
• 1996, membership in the Sigma Xi honor society.
• 1984, Graduated in top 2% (5th out of 250) from the Electronics and Communications Department at "Politehnica" University, Bucharest, Romania.
• 1980, 3rd prize at the Annual Students Conference, Bucharest, Romania, for "Flow Graphs for Electrical Circuit Analysis", (with Ioan Tache).

Graduate Students

Ph.D. students directed and graduated

1. Yan Zhang, Ph.D. dissertation: "Power-aware design in modern computing systems," December 2006, now with Qualcomm, San Diego, CA.
2. Wei Huang, Ph.D. dissertation: "Hotspot: a chip and package compact thermal modeling methodology for VLSI design," December 2006, now Researcher with the University of Virginia.
3. Garrett Rose, Ph.D. dissertation: "Design approaches for nanoscale circuits and architectures," August 2006, now Assistant Professor with Brooklyn Polytechnic, Brooklyn, NY.
4. Matthew Ziegler, Ph.D. dissertation: "Regularly Structured Design for Coping with Nanoscale Integration Complexity," August 2004, now with IBM TJ Watson Research Center, Yorktown Heights, NY.
5. Fatih Hamzaoglu, Ph.D. dissertation: "Low Power High Performance VLSI Design in Deep-Submicron CMOS", August 2002, now with Intel, Hillsboro, OR.
6. David Garrett, Ph.D. dissertation: "Power Reduction Techniques for VLSI Signal Processing Architectures", 2000, now with Broadcom, CA.

Ph.D. students directed in progress

1. Zhenyu Qi, Ph.D. expected May 2008, research in regular array circuits and SOC design.
2. Adam Cabe, Ph.D. expected May 2009, research in hybrid CMOS/molecular electronic circuits.

M.S. students directed and graduated

1. Yan Zhang, M.S. thesis: "Encoding for Low-Power I/O", August 2003, continued to Ph.D.
2. Garrett Rose, M.S. thesis: "Nanoelectronic device modeling for robust circuit design and analysis", May 2003, continued to Ph.D.
3. Marco Barcella, M.S. thesis: "Thermoelectric Cooling and Thermal Modeling for Integrated Circuits", August 2002, now with Appian Corporation, VA.
4. Joshua Garrett, M.S. thesis: "Temperature Analysis and Optimizations in High-Performance Low-Power VLSI", August 2001, now with Manhattan Routing, NY.
5. Avishek Panigrahi, M.S. thesis: "Noise analysis, immunity in high performance VLSI", August 2001, now with MIPS Technologies, Mountain View, CA.
6. Anshul Bhargava, M.S. thesis: "Optimizations and Analyses for High Speed VLSI Circuits", August 2001, now with MIPS Technologies, Mountain View, CA.
7. Arnaud Forestier, M.S. thesis: "Transistor and Circuit Optimization in VLSI Design", 1999, now with Intel, CA.
8. Abhimanyu Kolla, M.S. thesis: "Design and Implementation of an Integrated Multimicroelectrode Array for In-Vitro Neuronal Recording", August 1998, now with Intel, Dupont, WA.

M.S. students directed in progress

1. Dincer Unluer, M.S. expected May 2008, research in nanoelectronic circuits.

Ph.D. dissertation committee member

1. Karthik Sankaranarayanan, Ph.D. expected May 2008
2. Jeremy Sheaffer, May 2007
3. Zhijian Lu, "Runtime management techniques for power-and temperature-aware computing," December 2006
4. Yan Zhang, "Power-aware design in modern computing systems," December 2006
5. Wei Huang, "Hotspot: a chip and package compact thermal modeling methodology for VLSI design," December 2006
6. Yingmin Li, "Physically constrained architecture for chip multiprocessors," August 2006
7. Garrett Rose, "Design approaches for nanoscale circuits and architectures," August 2006
8. Michele Co, "Designing energy-efficient fetch engines," May 2006.
9. Matthew Ziegler, "Regularly Structured Design for Coping with Nanoscale Integration Complexity," August 2004
10. John Haskins, "Accelerating sampled microarchitecture simulation: rapid warm up for simulated hardware state," 2003
11. Fatih Hamzaoglu, "Low Power High Performance VLSI Design in Deep-Submicron CMOS", 2002
12. David Garrett, "Power reduction techniques for VLSI signal processing architectures", 2000
13. Munevver Kaya, "Flexible latency concatenated low complexity codes", 2000
14. Wuping Chen, "Wrist sensor for warfighter status monitor", 2000
15. Eric K. Hall, "Design and implementation of stream-oriented turbo codes", 1999
16. Ronald Hayne, "Behavioral fault modeling in a VHDL synthesis environment", 1999
17. Robert McGraw, "A system-level methodology and design environment for cycle-based systems", 1997

M.S. thesis committee member

1. Travis Lenhart, 2007
2. Eric Humenay, 2007
3. David Tarjan "Merging path, global and local indexing in perceptron branch prediction, 2006
4. Oguz Dogan, "Computation of mean time to first hazardous event," 2004
5. Jason Brandon, "A methodology for static leakage power reduction in SRAM-based FPGAs," 2004
6. Yingmin Li, 2004
7. Yan Zhang, "Encoding for Low-Power I/O", 2003
8. Garrett Rose, "Nanoelectronic device modeling for robust circuit design and analysis", 2003
9. Sheetal Chanderkhar, "Non-contacting CMOS readout circuit for an array of electrostatically levitated infrared sensors," 2003
10. Ram Surya Narayan, "Low power compact analog VLSI circuits for an adaptive multiplexed optical sensor system," 2003
11. Marco Barcella, "Thermoelectric Cooling and Thermal Modeling for Integrated Circuits", 2002
12. Amar Dwarka, "New design of an integrated microelectrode array for in vitro neural recording," 2002
13. Joshua Garrett, "Temperature Analysis and Optimizations in High-Performance Low-Power VLSI", 2001
14. Avishek Panigrahi, "Noise analysis, immunity in high performance VLSI", 2001
15. Anshul Bhargava, "Optimizations and Analyses for High Speed VLSI Circuits", 2001
16. Arnaud Forestier, "Transistor and Circuit Optimization in VLSI Design", 1999
17. Sreekanth Nallagatla, "Design of a GaAs integrated circuit for high frequency transceiver applications", 1998
18. Abhimanyu Kolla, "Design and Implementation of an Integrated Multimicroelectrode Array for In-Vitro Neuronal Recording", 1998

Undergraduate Students

Undergraduate theses supervised

1. Matthew Lindsay, senior thesis: "Temperature-aware interconnect sensors," 2007
2. Austin Kennedy, senior thesis: "Nanoelectronic analog-to-digital converter for nanoscale sensing systems," 2006
3. Samuel Sierra, senior thesis: "Analysis of three thermal sensors considered for use in a dynamic thermnal management processor," 2004
4. Brendan O'Brian, senior thesis: "Documentation of Gaisler Research SPARC V8 Compliant LEON2," 2004
5. Jonathan Kelly, senior thesis: "Nanomemory Scalability Simulation and Analysis," 2004
6. Irfan Ahmed, senior thesis: "Reduction of power dissipation in buses by implementing the bus-invert method," 2003
7. James Diersing, senior thesis: "Personal computer cooling modifications to improve performance and cost," 2002
8. Daniel Jones, senior thesis: "Optimization of a loadable asynchronous frequency divider with respect to clock frequency," 2002
9. David Lattimore, senior thesis: "Customized adder circuit for high performance and power conservation," 2002
10. Khanh Vu, senior thesis: "Optimizations for Copper Interconnect," 2001
11. Jay Ring, senior thesis: "A Stochastic Implementation of a Digital Neural Network," 2001
12. David Matthes, senior thesis: "High performance circuit design for a data path," 2000
13. Justin Strock, senior thesis: "Using Peltier Coolers to Decrease Power Consumption in Integrated Circuits," 2000
14. Paul Merolla, senior thesis: "Optimization of a multi-level inductor on a 0.18um process," 2000
15. Frank Van Deman, senior thesis: "Development of a Palm Pilot based wearable computer," 2000
16. Ryan Gates, senior thesis: Design, layout and simulation of a bi-directional shift register for use in a linear feedback shift register," 1999
17. Roger Lee, senior thesis: "State of the art report on nonvolatile memory," 1999
18. Douglas Madory, senior thesis: "Wearable computing," 1999
19. Sung Moon, senior thesis: "CMOS transistor design: building an array multiplier using donut-shaped transistor design to reduce power consumption," 1999
20. Jonathan Powers, senior thesis: "Design, verification, and testing of a bidirectional shift register," 1999
21. Andrew Slutter, senior thesis: "Development of a wearable computer system prototype emphasizing low coast and power consumption," 1999
22. Timothy Tan, senior thesis: "CMOS transistor design: building an array multiplier using the donut-shaped transistor design to reduce power consumption," 1999
23. Eric Ward, senior thesis: "Design of an EPROM," 1999
24. Paul Lappas, senior thesis: "Distributed memory M.I.M.D. architectures: design of a message-passing interface for the 35VEE8 processor," 1998
25. Arash Afrashteh, senior thesis: "Comparative analysis of ATM, FDDI, and Fast Ethernet in today's LAN," 1998
26. Darin Anderson, senior thesis: "Application of configurable computing techniques to general computing domains," 1998
27. Christopher Cassatt, senior thesis: "Cache coherency in shared memory multiprocessors," 1998
28. Loun-Loun Chua, senior thesis: "Adventures in microprocessor design: the 35VEE8," 1998
29. Christopher Collins, senior thesis: "Cache design: improved microprocessor performance through a tri-segmented integrated cache," 1998
30. Marc Monfalcone, senior thesis: "Design of the 35VEE8 microprocessor at the transistor level," 1998
31. Michael Storrs, senior thesis: "Design and simulation of a superscalar processor," 1998
32. Andrew Sugermeyer, senior thesis: "Frequency-adjustable digital guitar tuner: design and implementation," 1998
33. Jennifer Wilhelmi, senior thesis: "Microprocessor design: two-phase clocking in the 35VEE8 microprocessor," 1998
34. David Wilson, senior thesis: "35VEE8 processor: eliminating the stack," 1998
35. David Witter, senior thesis: "Adding floating-point operations to the 35VEE8 processor," 1998
36. John W. Walker, senior thesis: "Talisman Testing and Evaluation Software (TalEval): Future trends in hardware/software codesign," 1997

No. of Undergraduate Advisees (2007)

1. 11 Electrical Engineers
2. 7 Computer Engineers

Visitors and postdoc fellows

Postdocs supervised

1. Wei Huang, "Hotspot development", 2007-2010.

Exchange students supervised

1. Gregory Petit Dufrenoy, Belgium, technical report: "Sigma-Delta Modulator", 2000.
2. Alain Dannaoui, Switzerland, technical report: "Turbo Codes with reduced latency", 1998.
3. Andreas Semmler, Germany, technical report: "Underwater Body-LAN", 1997.

External Research Grants and Contracts

Funded research

1. Title: "Design and Analysis of Hybrid and Monolithic Molecular Systems"
   Sponsor: MARCO-IFC
   PI: Mircea Stan
   Duration: Oct. 2006 - Dec. 2009
   Amount: ~$360,000
2. Title: "SOC Design Methodology"
   Sponsor: Syracuse Research Corporation
   PI: Mircea Stan
   Duration: May 2007 - Sep. 2007
   Amount: $60,000
3. Title: "GPU/CPU Integration"
   PI: Kevin Skadron
   Co-PI: Mircea Stan
   Sponsor: SRC
   Duration: May. 2007 - Aug. 2010
   Amount: ~$150,000
4. Title: "DIALOGUE: Collaborative and Interactive Lectures and Design"
   PI: Mircea Stan
   Sponsor: HP
   Duration: Sep. 2006 - Aug. 2007
   Amount: ~$50,000 equipment, $15,000 cash
5. Title: "CRI: Comprehensive, Pre-RTL Architectural Thermal Modeling"
   PI: Kevin Skadron
   Co-PIs: Mircea Stan, Sudhanva Gurumurthy, Robert Ribando
   Sponsor: NSF
   Duration: Sep. 2006 - Aug. 2009
   Amount: ~$450,000, 1/4 for each Co-PI
6. Title: "Custom Design Tool for CMOL Circuits"
   PI: Mircea Stan
   Sponsor: ORNL
   Duration: Nov. 2005 - Dec. 2005
   Amount: $16,813
7. Title: "Physically Aware Computer Architecture"
   PI: Kevin Skadron
   Co-PIs: Mircea Stan, John Lach
   Sponsor: NSF
   Duration: Sep. 2004 - Aug. 2007
   Amount: ~$300,000, 1/3 for each Co-PI
8. Title: "Hybrid Mole Computer using Vapor Phase Assembly"
   PI: Lloyd Harriott
   Co-PIs: John Bean, Mircea Stan
   Sponsor: DARPA
   Duration: Jun. 2004 - Aug. 2006
   Amount: ~$1,000,000, 1/3 for each Co-PI
9. Title: "REU: Merged CMOS/Molecular Integrated Circuit (MolMOS) Fabrication, Analysis and Design"
   PI: Lloyd Harriott
   Co-PIs: Mircea R. Stan
   Sponsor: NSF
   Duration: Jun. 2003 - Aug. 2004
   Amount: $10,000, 1/2 for each Co-PI
10. Title: "NIRT: Merged CMOS/Molecular Integrated Circuit (MolMOS) Fabrication, Analysis and Design"
    PI: Lloyd Harriott
    Co-PIs: John Bean, Andrew Hillier, Lin Pu, Mircea R. Stan
    Sponsor: NSF
    Duration: Jun. 2002 - Aug. 2006
    Amount: $1,050,000, 1/5th for each Co-PI
11. Title: "CISE-RR: A High-Performance Shared-Purpose Cluster for Computer Architectural Simulation and Perceptual Interactive Ray Tracing"
    PI: David Luebke
    Co-PIs: Kevin Skadron, Mircea R. Stan
    Sponsor: NSF
    Duration: Sep. 2002 - Aug. 2004
    Amount: $72,802, 1/3rd for each Co-PI
12. Title: "REU: A High-Performance Shared-Purpose Cluster for Computer Architectural Simulation and Perceptual Interactive Ray Tracing"
    PI: David Luebke
    Co-PIs: Kevin Skadron, Mircea R. Stan
    Sponsor: NSF
    Duration: Sep. 2003 - Aug. 2004
    Amount: $15,000, 1/3rd for each Co-PI
13. Title: "FEST: Nanocircuit modeling and simulation", PI: Mircea R. Stan
    Sponsor: UVa
    Duration: Jun. 2002 - Aug. 2003
    Amount: $10,000
14. Title: "FEST: Temperature-aware computing", PI: Kevin Skadron
    Co-PI: Mircea R. Stan
    Sponsor: UVa
    Duration: Jun. 2002 - Aug. 2005
    Amount: $150,000, 1/2 for each Co-PI
15. Title: "CCR: Small-Scale Dynamic Reconfigurability for Large-Scale Benefits"
    PI: John Lach
    Co-PIs: Mircea Stan, Kevin Skadron
    Sponsor: NSF
    Duration: Sept. 2001 - Aug. 2004
    Amount: $400,000, 1/3 for each Co-PI
16. Title: "Sub-Volt CMOS circuits with reduced leakage"
    PI: Mircea Stan
    Sponsor: Intel Corp.
    Duration: Sept. 1999 - Aug. 2002
    Amount: $125,880
17. Title: "Low Power Design Techniques for ASIC DSP Cores"
    PI: Mircea Stan
    Sponsor: IBM Corp.
    Duration: Jan. 1999 - Aug. 2000
    Amount: $70,000
18. Title: "CAREER: Advances in Theory, Design Methods, and CAD for Low-Power VLSI"
    PI: Mircea Stan
    Sponsor: NSF
    Duration: Sep. 1997 - Aug. 2002
    Amount: $250,000
19. Title: "REU: VLSI Design for Low Power"
    PI: Mircea Stan
    Sponsor: NSF
    Duration: Sep. 1999 - Aug. 2002
    Amount: $5,000
20. Title: "REU: Low Power Library for Mentor Tools"
    PI: Mircea Stan
    Sponsor: NSF
    Duration: Sep. 1997 - Aug. 1999
    Amount: $5,000
21. Title: "Interfacing biological entities in-vitro with electronics: a CMOS integrated electrode array"
    PI: Erik Herzog
    Co-PI: Mircea Stan
    Sponsor: NIH
    Duration: Sep. 1998 - Aug. 2000
    Amount: $100,000, 1/2 for each Co-Pi
22. Title: "Schematic Driven Layout for Analog VLSI Design"
    PI: Mircea Stan
    Sponsor: Mentor Graphics Corp.
    Duration: Sep. 1997 - Aug. 1998
    Amount: $10,000

Pending proposals

Gifts

1. $15,000 from SRC in support of the HPLP SOC design activities, 2006
2. $15,500 in cash and $53,000 in equipment from HP in support of teaching activities, 2006
3. $7,000 from SRC in support of the HPLP SOC design activities, 2006
4. $50,000 from Intel MRL for "Temperature Adaptive Circuits", 2003, 2004
5. $40,000 from Intel MRL for "Active Cooling Adaptive Circuits", 2002
6. $57,000 from Lucent for "Concatenated Coding for Wireless Array Systems" (with prof. Stephen Wilson, 1/2 for each Co-PI), 2001
7. $8,000 unrestricted gift from SRC/Novellus for supporting the High Performance Low Power (HPLP) research program, 2001
8. 12 Dell PC workstations from Intel Corp. for supporting research in the HPLP lab, 1999-2002
9. Software licences valued at $25,000 from Microsoft Corp. for supporting research in the HPLP lab, 1999-2002

(f) Publications

Book section

1. Kevin Skadron, Mircea Stan, "Temperature Aware Computing," Morgan Kaufmann, to appear 2008.
2. Mircea R. Stan, Garrett Rose, Matthew Ziegler, "A Universal Device Model for Nanoelectronic Circuit Simulation," book chapter in "EMERGING BRAIN-INSPIRED NANO-ARCHITECTURES," Springer Verlag, V. Beiu, U. Rueckert editors, to appear 2007.
3. Mircea R. Stan, Garrett Rose, Matthew Ziegler, "Hybrid CMOS/Molecular Integrated Circuits," book chapter in "Moore’s Law: Beyond Planar Silicon CMOS and Into the Nano Era," Springer Verlag, Howard Huff editor, to appear 2007.
4. Mircea R. Stan, Wayne P. Burleson, "Bus-Invert Coding for Low-Power I/O", pp. 296-305, paper reprint in the book Low-power CMOS Design edited by Anantha Chandrakasan, Robert Brodersen, IEEE Press, 1998.

Refereed Journal papers

1. Z. Lu, W. Huang, M. R. Stan, K. Skadron, J. Lach, "Interconnect Lifetime Prediction for Reliability-Aware Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVSLI). Vol. 15, Issue 2, Feb. 2007, Page(s):159 - 172
2. G. Rose, Y. Yao, J. M. Tour, A. C. Cabe, N. Gergel-Hackett, N. Majumdar, J. C. Bean, L. R. Harriott, M. R. Stan, "Designing CMOS/Molecular Memories while Considering Device Parameter Variations," ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. , No. , 2007, Pages , in print.
3. W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, Kevin Skadron, Mircea Stan, "HotSpot: a compact thermal modeling methodology for early-stage VLSI design," IEEE Transactions on VLSI Systems, Volume 14, Issue 5, May 2006, Page(s):501 - 513
4. Wei Huang, Mircea Stan, Kevin Skadron, "Parameterized physical compact thermal modeling", IEEE Transactions on Components and Packaging Technologies, vol. 28, issue 4, pp. 615 - 622, Dec. 2005.
5. Zhijian Lu, John Lach, Mircea Stan, Kevin Skadron, "Improved thermal management with reliability banking", IEEE Micro, vol. 25, issue 6, pp. 40 - 49, Nov.-Dec. 2005.
6. K. Sankaranarayanan, M. R. Stan, K. Skadron, "A case for thermal-aware floorplanning at the microarchitecture level", Journal of Instruction-Level Parallelism, no. 8, 2005.
7. Garrett Rose, Matthew Ziegler, Mircea Stan, "A Large-Signal Two-Terminal Device Model for Nanoelectronic Circuit Analysis", IEEE Transactions on VLSI Systems, vol. 12, issue 11, pp. 1201 - 1208, Nov. 2004.
8. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, D. Tarjan, "Temperature-Aware Microarchitecture: modeling and implementation", ACM Transactions on Architecture and Code Optimization (TACO), pp. 94-125, Mar. 2004
9. Dharmesh Parikh, Kevin Skadron, Yan Zhang, Mircea R. Stan, "Power-Aware Branch Prediction: Characterization and Design", IEEE Transactions on Computers, vol. 53, issue 2, pp. 168-186, Feb. 2004.
10. Matthew Ziegler, Mircea Stan, "CMOS/nano Co-design for crossbar-based molecular electronic systems", IEEE Transactions on Nanotechnology, vol. 2, issue 4, pp. 217-230, Dec. 2003
11. Mircea R. Stan, Kevin Skadron, "Power-aware computing: Guest Editorial", IEEE Computer, vol. 36, issue 12, pp. 35-38, Dec. 2003.
12. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, D. Tarjan, "Temperature-aware computer systems: opportunities and challenges" IEEE Micro, vol. 23, issue 6, pp. 52-61, Nov.-Dec. 2003 - selected as a 2003 IEEE Micro Top Picks significant paper of the year in computer architecture.
13. Mircea Stan, Paul Franzon, Seth Goldstein, John Lach, Matthew Ziegler, "Molecular Electronics: From Devices and Interconnect to Circuits and Architecture", Proceedings of the IEEE, vol. 91, issue 11, pp. 1940-1957, Nov. 2003.
14. M. R. Stan, K. Skadron, M. Barcella, W. Huang, K. Sankaranarayanan, S. Velusamy, "HotSpot: a Dynamic Compact Thermal Model at the Processor-Architecture Level", Microelectronics Journal, vol. 34, pp. 1153-1165, 2003.
15. Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron, "Alloyed Branch History: Combining Global and Local Branch History for Robust Performance", International Journal on Parallel Processing, vol. 31, No. 2, pp. 137-177, Apr. 2003.
16. S. Vangal, N. Borkar, E. Seligman, V. Govindarajulu, V. Erranguntla, H. Wilson, A. Pangal, V. Veeramachaneni, M. Anders, J. Tschanz, Y. Ye, D. Somasekhar, B. Bloechel, G. Dermer, R. Krishnamurty, S. Narendra, M. Stan, S. Thompson, V. De, S. Borkar, "5GHz, 32-Bit Integer Execution Core in 130nm Dual-Vt CMOS", IEEE Journal of Solid-State Circuits, vol. 37, No. 11, pp. 1421-1432, Nov. 2002.
17. F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, V. De, "Analysis of Dual-VT SRAM Cells with Full-Swing Single-Ended Bit Line Sensing for On-Chip Cache", IEEE Transactions on VLSI Systems, vol. 10, no. 2, pp. 91-95, Apr. 2002.
18. Mircea R. Stan, "CMOS Circuits with Sub-Volt Supply Voltages", IEEE Design and Test of Computers, vol. 19, no. 2, pp. 34-43, March-April 2002.
19. Fatih Hamzaoglu, Mircea R. Stan, "Split-Path Skewed (SPS) CMOS Buffer for High Performance and Low Power Applications", IEEE Transactions on Circuits and Systems II, vol. 48, no. 10, pp. 998-1002, Oct. 2001.
20. Mircea R. Stan, "Low Power CMOS with Sub-Volt Supply Voltages", IEEE Transactions on VLSI Systems, vol. 9, no. 2, pp. 394-400, Apr. 2001.
21. Alvar Dean, David Garrett, Mircea R. Stan, Sebastian Ventrone, "Low Power Techniques for ASICs", VLSI Design Journal, pp. 317-331, Jun. 2001.
22. David Garrett, Mircea R. Stan, "Low Power Parallel Spread-Spectrum Correlator", IEE Proceedings on Circuits, Devices and Systems, pp. 191-196, Aug. 1999.
23. Mircea R. Stan, Alexandre F. Tenca, Milos D. Ercegovac, "Long and Fast Up/Down Counters", IEEE Transactions on Computers, pp. 722-735, Jul. 1998.
24. Mircea R. Stan, Wayne P. Burleson, "Low-Power Encodings for Global Communication in CMOS VLSI", IEEE Transactions on VLSI Systems, pp. 444-455, Dec. 1997.
25. Mircea R. Stan, Wayne P. Burleson, "Bus-Invert Coding for Low-Power I/O", IEEE Transactions on VLSI Systems, pp. 49-58, March 1995.
26. M. Stan, W. Burleson, C. Connolly, R. Grupen, "Analog VLSI for Robot Path-Planning", Journal of VLSI Signal Processing, vol. 8 (1), pp. 61-73, Jul. 1994.
27. M. Stan, W. Burleson, C. Connolly, R. Grupen, "Analog VLSI for Robot Path-Planning" (same paper as above), Analog Integrated Circuits and Signal Processing, vol. 6 (1), pp. 61-73, Jul. 1994.

Guest Editorship

1. Mircea R. Stan and Kevin Skadron, Guest Editors, "Power-aware Computing", IEEE Computer special issue on power-aware computing.

Magazine publications

1. Mircea R. Stan, "An ST506/ST412 Compatible Disk Drive", Electronic Engineering, Morgan Grampian, pp. 18, Aug. 1993.
2. Mircea R. Stan, "Programmable Logic Decodes Optical Encoders", Electronic Engineering, Morgan Grampian, pp. 37-38, June 1992.
3. Mircea R. Stan, "Modified Moebius Divide-by-N Counter with a 50% Duty Cycle", Electronic Engineering, Morgan Grampian, pp. 30-32, Sept. 1991.
4. Mircea R. Stan, "Shift Register Generators for Circular FIFOs", Electronic Engineering, Morgan Grampian, pp. 26-27, Feb. 1991.
5. Mircea R. Stan, "DMA Control for the Q-Bus", Electronic Engineering, Morgan Grampian, pp. 33, April 1990.
6. Mircea R. Stan, "Conditional Skip Manipulates Clock", EDN, Cahners, pp. 228, Dec. 6, 1990.

Tutorials and invited presentations

"Thermal modeling and thermal-aware design in nanotechnologies," Tutorial presentation (with Kaustav Banerjee, UC Santa Barbara, and Eric Pop, Illinois), GLSVLSI 2007, Stresa, Italy, 2007
2. "High-Performance Low-Power Circuits", Invited lecture, IBM, May 2006
3. "Hybrid CMOS/molecular ICs", Guest lecture, McGill University, Montreal, Canada, April, 2005
4. "Towards Practical Nanotechnology - Hybrid CMOS/molecular Integrated Circuits", full-day tutorial, Ecole Polytechnique de Montreal, Canada, April, 2005
5. "Power-Aware and Temperature-Aware Circuit design", Guest lecture, IEEE Santa Clara Valley - Solid-state Circuits Society, April, 2005
6. "Temperature-Aware Computing", Kyushu University, Japan, Distinguished IEEE CAS Lecture, Dec. 2004
7. "Temperature-Aware Computing", Fukuoka University, Japan, Distinguished IEEE CAS Lecture, Dec. 2004
8. "Thermal Management for Microprocessors", tutorial presentation (with Kevin Skadron, UVa, and David Brooks, Harvard), ISCA Conference, Munchen, Germany, June 2004
9. "Thermal Management Issues for Microprocessors", tutorial presentation (with Kevin Skadron, UVa, and David Brooks, Harvard), Micro-35 Conference, Istanbul, Turkey, Nov. 2002
10. "Sub-Volt Circuits with Multiple and Adaptive Threshold Voltages", invited presentation, Workshop on Low Power Circuits, Arlington, VA, Oct. 2001
11. "High-Performance Low-Power Buses", tutorial presentation (with C.K. Ken Yang, UCLA), ASIC/SOC 2000, Washington, DC, Sep. 16, 2000
12. "Low-Power Techniques in CMOS", invited seminar (with Wayne Burleson, ECE Dept., UMass/Amherst), Digital Semiconductor (since 1998 Compaq, currently Intel), Hudson, MA, Nov. 16, 1995
13. "Low Power Computing with I/O Encoding", invited seminar, State University of NY at Binghamton, NY, March 17, 1995

Major Conference papers

1. Y. Zhang, S. Gurumurthi, M. R. Stan, "SODA: Sensitivity Based Optimization of Disk Architecture," Design Automation Conference (DAC), San Diego, CA, June 2007 Page(s):865 - 870
2. M. R. Stan, A. Cabe, S. Ghosh, Z. Qi, "Teaching Top-Down ASIC/SoC Design vs Bottom-Up Custom VLSI," IEEE International Conference on Microelectronic Systems Education (MSE) June 2007 Page(s):89 - 90
3. Z. Qi, M. R. Stan, "Accurate Back-of-the-Envelope Transistor Model for Deep Sub-micron MOS," IEEE International Conference on Microelectronic Systems Education (MSE) June 2007 2007 Page(s):75 - 76
4. Z. Qi, M. Ziegler, S. Kosonocky, J. Rabaey, M. R. Stan, "Multi-Dimensional Circuit and Micro-Architecture Level Optimization," International Symposium on Quality Electronic Design (ISQED) San Jose, CA, March 2007 Page(s):275 - 280
5. Y. Zhang, M. R. Stan, "Temperature-aware circuit design using adaptive body biasing," Great lakes symposium on VLSI (GLSVLSI), Stresa-Lago Maggiore, Italy Pages: 84 - 89, 2007
6. M. Ziegler, G. S. Ditlow, S. V. Kosonocky, Z. Qi, M. R. Stan "Structured and tuned array generation (STAG) for high-performance random logic," Great lakes symposium on VLSI (GLSVLSI), Stresa-Lago Maggiore, Italy Pages: 257 - 262, 2007
7. Z. Lu, J. Lach, M. R. Stan, K. Skadron, "Design and Implementation of an Energy Efficient Multimedia Playback System," Asilomar Conference on Signals, Systems and Computers (ACSSC) Monterey, CA, Oct. 2006 Page(s):1491 - 1497
8. Z. Qi, W. Huang, A. Cabe, W. Wu, Y. Zhang, G. Rose, M. R. Stan, "A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors," IEEE International SOC Conference, Sept. 2006 Page(s):111 - 112
9. Mircea R. Stan, "Hybrid CMOS/molecular Electronic Circuits," Proceedings of the IEEE Nano Singapore Conference, Singapore, Jan. 2006.
10. Garrett Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, and James M. Tour, "Design Approaches for Hybrid CMOS/Molecular Memory based on Experimental Device Data", Great Lakes Symposium on VLSI (GLSVLSI), May 2006, Best paper award.
11. Zhijian Lu, Yan Zhang, John Lach, Kevin Skadron, Mircea R. Stan, "Procrastinating Voltage Scheduling with Discrete Frequency Sets", Design Automation and Test in Europe Conference (DATE), April 2006.
12. Mircea R. Stan, Garrett Rose, Matthew Ziegler, "Hybrid CMOS/molecular Electronic Circuits," Proceedings of the International Conference on VLSI Design, Hyderabad, India, Jan. 2006.
13. Siva Velusamy, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron, "Monitoring temperature in FPGA based SoCs" International Conference on Computer Design (ICCD), Oct. 2005.
14. Wei Huang, Eric Humenay, Kevin Skadron, Mircea R. Stan, "The need for a full-chip and package thermal model for thermally optimized IC designs", International Symposium on Low Power Electronics and Design (ISLPED) Aug. 2005.
15. Yan Zhang, Zhijian Lu, John Lach, Kevin Skadron, Mircea R. Stan, "Optimal procrastinating voltage scheduling for hard real-time systems", Design Automation Conference (DAC), June 2005.
16. Yan Zhang, Travis Blalock, Mircea R. Stan, "A three-level toggle-avoid bus signaling scheme", International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 2005.
17. Zhijian Lu, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron, "Interconnect Lifetime Prediction under Dynamic Stress for Reliability-Aware Design", IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 327-34, Nov. 2004.
18. Mircea R. Stan, Yan Zhang, "Perfect 3-limited-weight code for low power I/O", International workshop on power and timing modeling, optimization and simulation (PATMOS), pp. 79-89, Sep. 2004.
19. Lei He, Weiping Liao, Mircea R. Stan, "System Level Leakage Reduction Considering the Interdependence of Temperature and Leakage," Proceedings of the Design Automation Conference (DAC), San Diego, CA, Jun. 2004.
20. W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, S. Velusamy, "Compact Thermal Modeling for Temperature Aware Design," Proceedings of the Design Automation Conference (DAC), San Diego, CA, Jun. 2004.
21. Mircea R. Stan, "Systolic Counters with Unique Zero State", Proceedings of the International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, May 2004.
22. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, "Keynote: A Computer-Architecture Approach to Thermal Management in Computer Systems: Opportunities and Challenges" Proceedings of the International Conference on Thermal, Mechanical and Thermo-Mechanical Simulation and Experiments in Micro-electronics and Micro-systems (EUROSIME) Brussels, Belgium, May 2004, Keynote presentation for session.
23. Y. Li, D. Parikh, Y. Zhang, K. Sankaranarayanan, K. Skadron, M. R. Stan, "State-preserving vs. non-state-preserving leakage control in caches", Proceedings of the Design, Automation and Test in Europe Conference (DATE), Paris, France, Feb. 2004.
24. Matthew M. Ziegler, Mircea R. Stan, "A unified design space for regular parallel prefix adders", Proceedings of the Design, Automation and Test in Europe Conference (DATE), Paris, France, Feb. 2004.
25. Z. Lu, J. Lach, M. R. Stan, K. Skadron, "Reducing multimedia decode power using feedback control", Proceedings of the International Conference on Computer Design (ICCD), pp. 489-496, Oct. 2003.
26. Garrett S. Rose, and Mircea R. Stan, "Memory arrays based on molecular RTD devices", Proceedings of the IEEE Conference on Nanotechnology (IEEE-NANO), pp. 453-456, San Francisco, CA, Aug. 2003.
27. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, D. Tarjan, "Temperature-Aware Microarchitecture", Proceedings of the International Symposium on Computer Architecture (ISCA), San Diego, CA, June 2003, Best Paper award.
28. Marco Barcella, Mircea R. Stan, "MTCMOS with Outer Feedback (MTOF) Flip-Flops", Proceedings of the International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, May 2003.
29. Matthew M. Ziegler, Mircea R. Stan, "The CMOS/nano Interface from a Circuits Perspective", Proceedings of the International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, May 2003.
30. Matthew M. Ziegler and Mircea R. Stan, "A Case for CMOS/nano Co-design", Proceedings of the International Conference on Computer Aided Design (ICCAD), San Jose CA, Nov. 2002.
31. Z. Lu, J. Hein, M. Stan, J. Lach, K. Skadron and M. Humphrey, "Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads", Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Grenoble, France, Oct. 2002.
32. Fatih Hamzaoglu, Mircea R. Stan, "Circuit-Level Techniques to Control Gate Leakage for sub-100nm CMOS", Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED), Monterey, CA, Aug. 2002.
33. Y. Zhang, J. Lach, K. Skadron, and M. R. Stan, "Odd/Even Bus Invert with Two-Phase Transfer for Buses with Coupling", Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED), Monterey, CA, Aug. 2002.
34. Matthew M. Ziegler and Mircea R. Stan, "Design and Analysis of Crossbar Circuits for Molecular Nanoelectronics", Proceedings of the IEEE Conference on Nanotechnology (IEEE-NANO), Arlington VA, Aug. 2002.
35. Matthew M. Ziegler, Garrett S. Rose, and Mircea R. Stan, "A Universal Device Model for Nanoelectronic Circuit Simulation", Proceedings of the IEEE Conference on Nanotechnology (IEEE-NANO), Arlington VA, Aug. 2002.
36. Z. Lu, J. Hein, M. Humphrey, M. R. Stan, J. Lach, K. Skadron, "Control-Theoretic Dynamic Frequency and Voltage Scaling", Workshop on Self-Healing, Adaptive and self-MANaged Systems (SHAMAN),in conjunction with the ACM International Conference on Supercomputing (ICS), New York, NY, June, 2002, Best Paper award.
37. S. Vangal, N. Borkar, E. Seligman, V. Govindarajulu, V. Erranguntla, H. Wilson, A. Pangal, V. Veeramachaneni, M. Anders, J. Tschanz, Y. Ye, D. Somasekhar, B. Bloechel, G. Dermer, R. Krishnamurty, S. Narendra, M. Stan, S. Thompson, V. De, S. Borkar, "5GHz, 32-Bit Integer Execution Core in 130nm Dual-Vt CMOS", Proceedings of the International Solid-State Circuits Conference (ISSCC), Vol. 1, pp. 412-414, San Francisco, CA, Feb. 2002. Vol. 2, pp. 334-336, San Francisco, CA, Feb. 2002.
38. Mircea Stan, Avishek Panigrahi, "The Selective Pull-up (SP) Noise Immunity Scheme for Dynamic Circuits", Proceedings of the Design, Automation and Test in Europe Conference (DATE), Paris, France, Mar. 2002.
39. K. Skadron, T. Abdelzaher, M. R. Stan, "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management", Proceedings of the Conference on High Performance Computer Architecture (HPCA), Cambridge, MA, Feb. 2002.
40. D. Parikh, K. Skadron, Y. Zhang, M. Barcella, M. R. Stan, "Power Issues Related to Branch Prediction", Proceedings of the Conference on High Performance Computer Architecture (HPCA), Cambridge, MA, Feb. 2002.
41. Matthew Ziegler, Mircea R. Stan, "Flexible IP Blocks for Customized Synthesis", Proceedings of the ASIC/SOC 2001 Conference, Washington, DC, Sep. 2001.
42. David Garrett, Mircea R. Stan, "A 2.5Mb/s, 23mW SOVA Traceback Chip for Turbo Decoding Applications", Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 61-64, Sydney, Australia, May, 2001.
43. Joshua Garrett, Mircea R. Stan, "Active Threshold Compensation Circuit for Improved Performance in Cooled CMOS Systems", Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 410-413, Sydney, Australia, May, 2001.
44. Matthew Ziegler, Mircea R. Stan, "Optimal Logarithmic Adder Structures with a Fanout of Two for Minimizing the Area-Delay Product", Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 657-660, Sydney, Australia, May, 2001.
45. M. Ziegler, A. Spanberger, G. Pai, M. R. Stan, K. Skadron, "Dynamic Way Allocation for High Performance, Low Power Caches", PACT 2001: International Conference on Parallel Architectures and Compilation Techniques, WiP session, Barcelona, Spain, September 8-12, 2001. Published in the IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, pp. 14-15, Oct. 2001.
46. Y. Ye, J. Tschanz, S. Narendra, S. Borkar, M. Stan, V. De, "Comparative Delay, Noise, and Energy of High-Performance Domino Adders with Stack Node Preconditioning (SNP)", Proceedings of the VLSI Circuits Symposium, pp. 188-191, Honolulu, Hawaii, Jun. 2000.
47. F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, V. De, "Dual-VT SRAM Cells with Full-Swing Single-Ended Bit Line Sensing for High-Performance On-Chip Cache in 0.13 um Technology Generation", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 15-19, Rapallo, Italy, Jul. 2000.
48. Arnaud Forestier, Mircea R. Stan, "Limits to Voltage Scaling from a Low Power Perspective", Proceedings of the Symposium on Integrated Circuits and System Design, pp. 365-370, Manaus, Brazil, Sept. 2000.
49. David Garrett, Alvar Dean, Mircea R. Stan, "Challenges in Clock Gating for Low Power for ASIC Cores", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 176-181, San Diego, CA, Aug. 1999.
50. Mircea R. Stan, "Optimal Voltages and Sizing for Low Power", Proceedings of the International Conference on VLSI Design, pp. 428-433, Goa, India, Jan. 1999.
51. Arnaud Forestier, Mircea R. Stan, "Low-Power Four-Quadrant Multiplier using Dual-Gate Transistors", Proceedings of the International Symposium on Circuits and Systems (SCS), pp. 29-32, Iasi, Romania, Aug, 1999.
52. Mircea R. Stan, "Low-Threshold CMOS Circuits with Low Standby Current", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 97-99, Monterey, CA, Aug. 1998.
53. David Garrett, Mircea R. Stan, "Low-Power Architecture for the Soft-Output Viterbi Algorithm", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 262-267, Monterey, CA, Aug. 1998.
54. Mircea R. Stan, "Low Power Encodings and ECC Duals", Proceedings of the International Symposium on Information Theory (ISIT), pp. 19, Boston, MA, Aug. 1998.
55. Abhimanyu Kolla, Mircea R. Stan, Erik Herzog, Suzanne Moenter, "Integrated Planar Multimicroelectrode Array for In Vitro Recording", Proceedings of the Asilomar Conference on Computers, Signals and Systems, pp. 1537-1541, Pacific Grove, CA, Nov. 1997.
56. David Garrett, Mircea R. Stan, "Power Reduction Techniques for a Spread Spectrum Correlator", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 225-230, Monterey, CA, Aug. 1997.
57. Mircea R. Stan, "Synchronous Up/Down Counter with Clock Period Independent of Counter Size", Proceedings of the IEEE Symposium on Computer Arithmetic (ARITH), pp. 274-281, Asilomar, CA, July 1997.
58. Mircea R. Stan, Wayne P. Burleson, "Two-dimensional Codes for Low-Power", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 335-340, Monterey, CA, Aug. 1996.
59. Mircea R. Stan, Wayne P. Burleson, "Coding a Terminated Bus for Low-Power", Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), pp. 70-73, Buffalo, NY, March 1995.
60. Mircea R. Stan, Wayne P. Burleson, "Analog VLSI for Robot Path-Planning", Proceedings of the Asilomar Conference on Computers, Signals and Systems, Pacific Grove, CA, 1992.

Minor conference papers

1. Z. Lu, J. Lach, M. Stan, K. Skadron, "Banking Chip Lifetime: Opportunities and Implementation", Workshop on High Performance Computing Reliability Issues (HPCRI), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture, Feb. 2005.
2. S. Velusamy, W. Huang, J. Lach, M. Stan, K. Skadron, "Experiences using FPGAs for Temperature-Aware Microarchitecture Research", Workshop on Architecture Research using FPGA Platforms (WARFP), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture, Feb. 2005.
3. W. Huang, M. R. Stan, K. Skadron, "Physically-Based Compact Thermal Modeling—Achieving Parameterization and Boundary Condition Independence", International Workshop on Thermal Investigations of ICs (THERMINIC), Sept. 2004, pp. 287-92.
4. D. Tarjan, K. Skadron, M.R. Stan, "An Ahead Pipelined Alloyed Perceptron with Single Cycle Access Time", Workshop on Complexity Effective Design (WCED), in conjunction with the 31st International Symposium on Computer Architecture (ISCA), June 2004.
5. D. Parikh, Y. Zhang, K. Sankaranarayanan, K. Skadron, M. Stan "Comparison of State-Preserving vs. Non-State-Preserving Leakage Control in Caches" Second Annual Workshop on Duplicating, Deconstructing, and Debunking in conjunction with ISCA-30, June 2003.
6. M.R. Stan, K. Skadron, "Teaching Processor Architecture with a VLSI Perspective", Workshop on Computer Architecture Education, in conjunction with ISCA-29, May 2002.
7. M. Ziegler, A. Spanberger, G. Pai, M. Stan, K. Skadron, "Dynamic Way Allocation for High Performance, Low Power Caches", Work-in-Progress Session at the 2001 International Conference on Parallel Architectures and Compilation Techniques, Sept. 2001. Also appears in Newsletter of the IEEE Technical Committee on Computer Architecture, pp. 14-15, Oct. 2001.
8. Tarek Abdelzaher, Mircea R. Stan, "Temperature-Adaptive Sensor Networks (TASN) for Harsh Environments," Midwest Symposium on Circuits and Systems (MWSCAS), Cairo, Egypt, Dec. 2003.
9. K. Skadron, M. Barcella, W. Huang, K. Sankaranayaranan, S. Velusamy, M. R. Stan, "HotSpot: Techniques for Modeling Thermal Effects at the Processor-Architecture Level", International Workshop on THERMal Investigations of ICs and Systems (THERMINIC), Madrid, Spain, October 2002.
10. Mircea R. Stan, Kevin Skadron, "Teaching Processor Architecture with a VLSI Perspective", Workshop on Computer Architecture Education (WCAE), in conjunction with the International Symposium on Computer Architecture (ISCA), Anchorage, AK, May 26, 2002.
11. M. Ziegler, A. Spanberger, G. Pai, M. R. Stan, K. Skadron, "Dynamic Way Allocation for High Performance, Low Power Caches", Work-in-Progress Session at the International Conference on Parallel Architectures and Compilation Techniques, September, 2001. Also appears in Newsletter of the IEEE Technical Committee on Computer Architecture, pp. 14-15, October, 2001.
12. Mircea R. Stan, "A Scaling Scenario for Nanoelectronic Technologies", Georgia Tech Conference on Nanoscience and Nanotechnology, pp. 104, Atlanta, GA, Sept. 2001.
13. Matthew Ziegler, Mircea R. Stan, "Silicon and Molecular Electronics in terms of Information Processing Density", Georgia Tech Conference on Nanoscience and Nanotechnology, pp. 103, Atlanta, GA, Sept. 2001.
14. M. Holzer, A.J. Nijdam, A. Kolla, G. Block, M. Geusz, E. Herzog, M. R. Stan, T. Blalock, W.-K. Lye, Y. Zu, M. L. Reed, "Integrated Microelectrode Arrays for In Vitro Neuronal Recording", poster, Biomedical Engineering Society Meeting, Annals of Biomedical Engineering, Vol 28, Supplement 1, 2000.
15. Alvar Dean, Sebastian Ventrone, David Garrett, Mircea R. Stan, "C54XDSP ASIC Core Low Power Experiences", High Speed VLSI Power Workshop, IBM Research, Yorktown Heights, NY, Aug. 1999.
16. Mircea R. Stan, Rama R. Kotapally, Andrew Slutter, "Op-Amps as Firm Virtual Components for Systems-on-Chip", Proceedings of the IEEE Workshop on VLSI (IWV), pp. 54-59, Orlando, Florida, Apr. 1999.
17. Mircea R. Stan, "Experiences with a Schematic-Driven Layout Package for Mixed-Signal CMOS Design", Southeastern Workshop on Mixed-Signal VLSI and Monolithic Sensors, Oak-Ridge National Lab (ORNL), TN, 1998.
18. David Garrett, Joshua Garrett, Mircea R. Stan, "Low-Power Design Environment for MOSIS", Mentor Graphics Users' Group Conference (MUG), Portland, OR, Oct. 1997.
19. Mircea R. Stan, David Garrett, Abhimanyu Kolla, Zaid Salman, "Schematic Driven Layout Using the MOSIS Design Kit for Advanced Analog and Mixed-Signal Design", Mentor Graphics Users' Group Conference (MUG), Portland, OR, Oct. 1997.
20. Mircea R. Stan, Wayne P. Burleson, "Synchronous Up/Down Counter with Period Independent of Counter Size", poster, ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, Feb. 1996.
21. Mircea R. Stan, Wayne P. Burleson, "Low-power CMOS Clock Drivers", Proceedings of the International Workshop on Timing Issues (TAU), pp. 149-156, Seattle, WA, Nov. 1995.
22. Mircea R. Stan, Wayne P. Burleson, "Limited-Weight Codes for Low-Power I/O", Proceedings of the International Workshop on Low Power Design (IWLPD), pp. 209-214, Napa, CA, April 1994.
23. Mircea R. Stan, Sorin Guiman, "Firmware for Intelligent Peripheral Controllers - a Case Study of Real-Time Programming for Embedded Systems", IFAC/IFIP Workshop on Real-Time Programming (WRTP), Berlin, Germany, 1989.
24. Mircea R. Stan, "A New Structural Solution for Designing a PC Disk-Drive Controller", Symposium on Informatics (CONDINF), Cluj, Romania, 1989.
25. Mircea R. Stan, Sorin Guiman, "Microprogrammed Structure for Interfacing High-Performance Disk Drives to a Minicomputer System", National Symposium for Computers and Automation (SCA), Timisoara, Romania, 1988.
26. Mircea R. Stan, Gabriel Mateescu, "Intelligent Microprogrammed Controllers for Streaming Tape and Performant Disk Drives", Information Technology Advances in Computer Science Conference (INFOTEC), Bucharest, Romania, 1988.

Technical reports

1. W. Huang, Z. Lu, S. Ghosh, J. Lach, M. R. Stan, K. Skadron, "The Importance of Temporal and Spatial Temperature Gradients in IC Reliability Analysis", Tech Report CS-2004-07, University of Virginia, Jan. 2004.
2. Z. Lu, M. R. Stan, J. Lach, K. Skadron, "Interconnect Lifetime Prediction for Temperature-Aware Design", Tech Report CS-2003-21, University of Virginia, Nov. 2003.
3. Y. Li, M. R. Stan, K. Skadron, "New Findings on Using Queue Occupancy to Integrate Runtime Power-Saving Techniques Across the Pipeline", Tech Report CS-2003-15, University of Virginia, July 2003.
4. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, D. Tarjan, "Temperature-Aware Microarchitecture: Extended Discussion and Results", Tech Report CS-2003-08, University of Virginia, April 2003.
5. Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, M. R. Stan. "HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects", Tech Report CS-2003-05, University of Virginia, March 2003.
6. Z. Lu, J. Lach, M. R. Stan, K. Skadron, "Alloyed Branch History: Combining Global and Local Branch History for Robust Performance", Tech Report CS-2002-21, University of Virginia, July 2002.
7. M. Barcella, W. Huang, M. R. Stan, K. Skadron, "Architecture-Level Compact Thermal R-C Modeling", Tech Report CS-2002-20, University of Virginia, July 2002.
8. K. Skadron, T. Abdelzaher, M. R. Stan, "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management", Tech Report CS-2001-27, University of Virginia, November 2001.
9. D. Parikh, K. Skadron, Y. Zhang, M. Barcella, M. R. Stan, "Power Issues Related to Branch Prediction" Tech Report CS-2001-25, University of Virginia, November 2001.

Public reviews published in magazines

These are published (not confidential) reviews about recent publications (books or papers) in order to help readers and libraries decide whether to acquire them. All are published in the well known ACM Computing Reviewsmagazine.

1. Published comparative review of 6 books: "Circuit Synthesis with VHDL" by R. Airiau, J.-M. Berge and V. Olive, "Structured Logic Design with VHDL" by J. R. Armstrong and F. G. Gray, "VHDL Programming with Advanced Topics" by L. Baker, "A VHDL primer" by J. Bhasker, "A Designer's Guide to VHDL Synthesis" by D. E. Ott and T. J. Wilderotter and "VHDL" by D. L. Perry, ACM Computing Reviews, Mar. 1996.
2. Published review of book "AS/400 Security in a Client/Server Environment" by J. S. Park, ACM Computing Reviews, June 1996.
3. Published review of book "A Guide to VHDL Syntax: Based on the New IEEE Std 1076-1993" by J. Bhasker, ACM Computing Reviews, Feb. 1996.
4. Published review of journal paper "Set-associative cache simulation using generalized binomial trees" by R. A. Sugumar and S. G. Abraham, ACM Computing Reviews, Feb. 1996.
5. Published review of journal paper "A design system for on-chip oversampling A/D interfaces" by M. F. Mar and R. Brodersen, ACM Computing Reviews, June 1996.
6. Published review of journal paper "A simplified design strategy for mapping image processing algorithms on a SIMD torus" by G. Seetharaman, ACM Computing Reviews, Aug. 1996.
7. Published review of journal paper "Using visual texture for information display" by C. Ware and W. Knight, ACM Computing Reviews, Dec. 1995.
8. Published review of journal paper "Pulse stream VLSI neural networks" by A. F. Murray, S. Churcher, A. Hamilton, A. J. Andrew, ACM Computing Reviews, Mar. 1995.
9. Published review of book "Digital Design using ABEL" by D. Pellerin and M. Holley, ACM Computing Reviews, Feb. 1995.
10. Published review of book "Discrete Iterated Function Systems" by M. Perrugia, ACM Computing Reviews, Nov. 1994.
11. Published review of book "Contemporary Logic Design" by Randy H. Katz, ACM Computing Reviews, Oct. 1994.
12. Published review of book "PSpice with Circuit Analysis" by F. Monssen, ACM Computing Reviews, Jul. 1994.
13. Published review of journal paper "Reliability, reconfiguration, and spare allocation issues in binary-tree architectures based on multiple-level redundancy" by Y.-Y. Chen and S. J. Upadhyaya, ACM Computing Reviews, Jul. 1994.
14. Published review of book "An Introduction to Systolic Algorithm Design" by G. M. Megson, ACM Computing Reviews, Jan. 1994.
15. Published review of book "A Contour-Oriented Approach to Shape Analysis" by P. J. van Otterloo, ACM Computing Reviews, Dec. 1993.
16. Published review of book "Circuit Design for CMOS VLSI" by J. P. Uyemura, ACM Computing Reviews, Sep. 1993.
17. Published review of journal paper "VLSI implementation of a stochastic database machine for relational algebra and hashing" by L. M. Delcambre, M. A. Bayoumi and K. M. Elleithy, ACM Computing Reviews, Oct. 1992.
18. Published review of the April, 1992 IEEE Computer Journal special issue on Wafer-Scale Integration (WSI), ACM Computing Reviews, Jul. 1993.
19. Published review of book "Representations of Musical Signals" by G. de Poli and A. Piccialli, ACM Computing Reviews, Apr. 1993.
20. Published review of book "Understanding Digital Electronics" by M. J. Sanfilipo, ACM Computing Reviews, Dec. 1990.

Citations

The top-10 most cited papers on which I am an author have more than 3000 citations as reported by Google Scholar: Overall there are about 5000 citations to papers on which I am an author and my h-index is 34.

• Mircea R. Stan, Wayne P. Burleson, "Bus-Invert Coding for Low-Power I/O", IEEE Transactions on VLSI Systems, pp. 49-58, March 1995. Cited by 721
• K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, D. Tarjan, "Temperature-Aware Microarchitecture", Proceedings of the International Symposium on Computer Architecture (ISCA), San Diego, CA, June 2003, Best Paper award. Cited by 712
• K. Skadron, T. Abdelzaher, M. R. Stan, "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management", Proceedings of the Conference on High Performance Computer Architecture (HPCA), Cambridge, MA, Feb. 2002. Cited by 276
• Mircea R. Stan, Wayne P. Burleson, "Low-Power Encodings for Global Communication in CMOS VLSI", IEEE Transactions on VLSI Systems, pp. 444-455, Dec. 1997. Cited by 93
• D. Parikh, K. Skadron, Y. Zhang, M. Barcella, M. R. Stan, "Power Issues Related to Branch Prediction", Proceedings of the Conference on High Performance Computer Architecture (HPCA), Cambridge, MA, Feb. 2002. Cited by 73
• W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, Kevin Skadron, Mircea Stan, "HotSpot: a compact thermal modeling methodology for early-stage VLSI design," IEEE Transactions on VLSI Systems, Volume 14, Issue 5, May 2006, Page(s):501 - 513 Cited by 69
• Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, M. R. Stan. "HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects", Tech Report CS-2003-05, University of Virginia, March 2003. Cited by 65
• Mircea R. Stan, Wayne P. Burleson, "Limited-Weight Codes for Low-Power I/O", Proceedings of the International Workshop on Low Power Design (IWLPD), pp. 209-214, Napa, CA, April 1994. Cited by 62
• Mircea Stan, Paul Franzon, Seth Goldstein, John Lach, Matthew Ziegler, "Molecular Electronics: From Devices and Interconnect to Circuits and Architecture", Proceedings of the IEEE, vol. 91, issue 11, pp. 1940-1957, Nov. 2003. Cited by 56
• Fatih Hamzaoglu, Mircea R. Stan, "Circuit-Level Techniques to Control Gate Leakage for sub-100nm CMOS", Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED), Monterey, CA, Aug. 2002. Cited by 50

Patents

Patent awarded

1. James W. Tschanz, Mircea R. Stan, Siva G. Narendra, Vivek De, "Temperature dependent regulation of threshold voltage", US 6,917,237, Jul. 12, 2005, Intel.
2. Mircea R. Stan, Vivek De, "Dynamic CMOS Circuits with Individually Adjustable Noise Immunity", US 6,710,627, Mar. 23, 2004, Intel.
3. Mircea R. Stan, James Jasmin, "Multi-Threshold CMOS flip-flop with outside feedback", US 6,538,471, Mar. 25, 2003, IBM.
4. Mircea R. Stan, Vivek De, "Dynamic CMOS Circuits with Individually Adjustable Noise Immunity", US 6,518,796, Feb 11, 2003, Intel.
5. David Garrett, Alvar Dean, Mircea R. Stan, "Methods for Improving the Efficiency of Clock Gating within Low Power Clock Trees", US 6,434,704, Aug. 13, 2002, IBM.

Patent disclosures

1. Mircea R. Stan, "Parallel algorithm and structure for decoding parallel or serial concatenated codes (Turbo codes), 2000, UVa.
2. Mircea R. Stan, Suzanne Moenter, Abhimanyu Kolla, Erik Herzog, Gene Block, Alan Batson, Michael Geusz, "Addressable Array of Microelectrodes with Embedded Electronics for Neural Recording", 1998, UVa.

Service

Consulting History

• 2003-present, Gerson Lehrman Group Technology Council, New York, NY, Duties: Industry-wide surveys, specific company-related market data
• 1999-present, National Science Foundation, Arlington, VA, Duties: Peer review of research proposals
• 2005, Oak Ridge National Lab, Oak Ridge, TN, Duties: Organized workshop on Nanotechnology, prepared reports, roadmap activities, presentations
• 2003, U.S. Civilian Research and Development Foundation, Arlington, VA, Duties: Reviewed international funding proposal
• 2003, Research Council of Norway, Norway Duties: Reviewed national technical funding proposal
• 2002, Ultimit Solutions, Inc., Northern Virginia, Duties: Defined technical specifications for new product
• 1999-2002, Intel, Portland, OR, Duties: High performance circuit design for microprocessors

Litigation Support Experience

• 2004, Reed Smith, Case: Xybernaut v. Viewsonic, Project: Expert Report for Patent Infringement case Status: Settled

Service to the University

• 1998-present: Faculty advisor for the IEEE student chapter at UVa.
• 2000-2002: Faculty marshal for Unversity graduation ceremony.
• 1997-2004: University of Virginia Campus representative for USENIX, the Advanced Computing Systems Association.

Service to the School of Engineering

• 2002-2004: Chair of the Computing Environment Committee for SEAS.
• 2000-2002: Faculty marshal for SEAS graduation ceremony.
• 1999-2004: Common Reading Experience committee member.
• 2003-2004: Computing Environment committee chair.
• 1998-2002: Computing Environment committee member.
• 1998-1999: Undergraduate Curriculum Committee member.

Service to the ECE Department

• 2007: Host for Prof. Keshab Parhi, eminent speaker from University of Minnesota
• 2006: Host for Dr. Pranav Ashar, eminent speaker from NEC Labs
• 2006: Host for Dr. Vassily Moshnyaga, eminent speaker from Fukuoka University
• 2005-2006: Faculty advisor for student team participating in "SOC Design Contest" organized by SRC
• 2005-present: Graduate Committee
• 2003-2004: Computer Engineering Undergraduate Committee
• 2003-present: Graduate Recruiting Committee
• 2003-2004: Undergraduate Enrichment Committee
• 2003: Host for Dr. Stephen Kossonocky, invited speaker from IBM
• 2002-2003: Faculty advisor for student team participating in "SiGe Design Contest" organized by SRC
• 1998-2003: Chair of the Computing Resources Committee for ECE
• 1998-2003: Eminent Speakers Committee member
• 1998-1999, 2001-2003: Graduate Committee member
• 2000-2001: Hiring Committee member for ECE department system administrator
• 2001-2002: Faculty advisor for student team participating in the 2002 "International Design Competition (CSIDC)" organized by the IEEE Computer Society
• 2000-2001: Faculty advisor for student team participating in the 2001 "International Design Competition (CSIDC)" organized by the IEEE Computer Society
• 2000: Host for Dr. Vivek De, invited speaker from Intel
• 1999-2000: Faculty advisor for student team participating in "Cu Design Challenge" contest organized by SRC
• 1999-2000: Undergraduate Committee member
• 1998-1999, 2001-present: Ph.D. Qualifying exam Committee member

Professional societies

• Senior member of the IEEE the Institute of Electrical and Electronics Engineers.
• Member of the IEEE Solid-State Circuits Society
• Member of the IEEE Circuits and Systems Society
• Member of the IEEE Electron Devices Society
• Member of the IEEE Communications Society
• Past member of the IEEE Information Theory Society
• Member of the IET the Institution of Engineering and Technology (former IEE)
• Member of ACM, the Association for Computing Machinery
• Member of SIGDA, the ACM Special Interest Group on Design Automation.

Service to the profession

• Proposal reviewer and panel member for the National Science Foundation (NSF)

Journal editor

• 2003-present: Associate Editor for the IEEE Transactions on Circuits and Systems
• December 2003: Guest Editor for the IEEE Computer special issue on Power-Aware Computing
• 2000-2003: Associate Editor for the IEEE Transactions on VLSI Systems

Journal reviewer

• Reviewer for the IEEE Transactions on VLSI Systems.
• Reviewer for the IEEE Transactions on CAD.
• Reviewer for the IEEE Transactions on Circuits and Systems.
• Reviewer for the IEE Electronics Letters.
• Reviewer for the IEEE Transactions on Computers.
• Reviewer for the IEEE Journal of Solid-State Circuits.
• Reviewer for the VLSI Journal.
• Reviewer for the Journal of VLSI Signal Processing.

Conference chair

• Technical Program chair for the International Conference on Nano-Networks (NanoNets), Catania, Italy, 2007
• General chair for the International Symposium on Low Power Electronics and Design (ISLPED), Tegernsee, Germany, 2006
• Technical Program chair for the International Symposium on Low Power Electronics and Design (ISLPED), San Diego, CA, 2005
• General chair for the Great Lakes Symposium on VLSI (GLSVLSI), Washington, DC, 2003
• Publicity chair for the International Symposium on Low Power Electronics and Design (ISLPED), Monterey, California, 1998

Conference committee member

• Technical committee member for the IEEE Workshop on Signal Processing Systems (SiPS), Shanghai, China, 2007
• Technical committee member for the European Conference on Circuit Theory and Design (ECCTD), Sevilla, Spain, 2007
• Technical committee member for the IEEE Computer Society Symposium on VLSI (ISVLSI), Porto Alegre, Brazil, 2007
• Technical committee member for the Design, Automation and Test in Europe Conference (DATE), Nice, France, 2007
• Technical committee member for the International Symposium on Circuits and Systems (ISCAS), New Orleans, LA, 2007
• Technical committee member for the Great Lakes Symposium on VLSI (GLSVLSI), Stresa, Italy, 2007
• Technical committee member for the International Conference on Nano-Networks (NANO-NET), Lausanne, Switzerland, 2006
• Technical committee member for the International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH), Boston, MA, 2006
• Technical committee member for the Workshop on Temperature-Aware Computer Systems (TACS), Boston, MA, 2006
• Technical committee member for the International Conference on CAD (ICCAD), San Jose, CA, 2006
• Technical committee member for the Great Lakes Symposium on VLSI (GLSVLSI), Philadelphia, PA, 2006
• Technical committee member for the International Symposium on Circuits and Systems (ISCAS), Kos, Greece, 2006
• Technical committee member for the Workshop on Temperature-Aware Computer Systems (TACS), Palm Springs, CA, 2005
• Technical committee member for the Great Lakes Symposium on VLSI (GLSVLSI), Chicago, IL, 2005
• Technical committee member for the International Symposium on Low Power Electronics and Design (ISLPED), San Diego, CA, 2005
• Technical committee member for the International Symposium on Low Power Electronics and Design (ISLPED), Newport Beach, CA, 2004
• Technical committee member for the IEEE SOC Conference, San Jose, CA, 2004
• Technical committee member for the International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, 2004
• Technical committee member for the Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA, 2004
• Technical committee member for the Design, Automation and Test in Europe Conference (DATE), Paris, France, 2004.
• Technical committee member for the International Conference on Computers and Design (ICCD), San Jose, CA, 2003.
• Technical committee member for the IEEE SOC Conference, Portland, OR, 2003
• Technical committee member for the International Symposium on Low Power Electronics and Design (ISLPED), Seoul, Korea, 2003
• Technical committee member for the International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, 2003
• Technical committee member for the Great Lakes Symposium on VLSI (GLSVLSI), Washington, DC, 2003
• Technical committee member for the Design, Automation and Test in Europe Conference (DATE), Munich, Germany, 2003
• Technical committee member for the IEEE ASIC/SOC Conference, Rochester, NY, 2002
• Technical committee member for the International Symposium on Low Power Electronics and Design (ISLPED), Monterey, California, 2002.
• Technical committee member for the Design, Automation and Test in Europe Conference (DATE), Paris, France, 2002
• Technical committee member for the International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, 2002
• Technical committee member for the Great Lakes Symposium on VLSI (GLSVLSI), New York, NY, 2002
• Technical committee member for the IEEE ASIC/SOC Conference, Washington, DC, 2001
• Technical committee member for the International Symposium on Low Power Electronics and Design (ISLPED), Huntington Beach, California, 2001.
• Technical committee member for the Conference on Advanced Research in VLSI (ARVLSI), Salt Lake City, Utah, 2001.
• Technical committee member for the International Conference on VLSI Design, Calcutta, India, 2000.
• Technical committee member for the International Symposium on Low Power Electronics and Design (ISLPED), Rapallo, Italy, 2000.
• Technical committee member for the International Symposium on Low Power Electronics and Design (ISLPED), San Diego, California, 1999.
• Technical committee member for the International Conference on VLSI Design, Goa, India, 1999.
• Technical committee member for the International Symposium on Low Power Electronics and Design (ISLPED), Monterey, California, 1998.
• Technical committee member for the International Conference on VLSI Design, Chennai, India, 1998.

Other conference organization

• Session Chair at the International Symposium on Circuits and Systems (ISCAS), Kos, Greece, 2006.
• Session Chair at the Great Lakes Symposium on VLSI (GLSVLSI), Philadelphia, PA, 2006.
• Session Chair at the International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, 2005.
• Panelist at the International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH), Palm Springs, CA, 2005.
• Session Chair at the International Symposium on Circuits and Systems (ISCAS), Vancouver, CA, 2004.
• Session Chair at the Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA, 2004. Design, Automation and Test in Europe Conference (DATE), Paris, France, 2004.
• Session Chair at the International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, 2003.
• Session Chair at the Design, Automation and Test in Europe Conference (DATE), Paris, France, 2002.
• Session Chair at the Great Lakes Symposium on VLSI (GLSVLSI), New York, NY, 2002.
• Session Chair at the International Symposium on Circuits and Systems (ISCAS), Sydney, Australia, 2001.
• Session Chair at the International Symposium on Low Power Electronics and Design (ISLPED), Huntington Beach, California, 2001.
• Reviewer for the International Symposium on Signals, Circuits and Systems (SCS), Iasi, Romania, 2001.
• Session Chair at the IFIP International Conference on VLSI, Lisbon, Portugal, 1999.
• Organizer of special session on low-power at the International Symposium on Signals, Circuits and Systems (SCS), Iasi, Romania, 1999.

Courses Taught

• Fall 2007: ECE230 - Digital Logic Design
• Spring 2007: ECE436 - Advanced Digital Design
• Fall 2006: ECE686 - SOC Design
• Spring 2006: ECE436 - Advanced Digital Design
• Spring 2006: ECE687 - Physically-Aware Design
• Fall 2005: ECE563 - VLSI Design - A Top-Down Perspective
• Spring 2004: ECE/CS230 - Digital Logic Design
• Spring 2004: ECE786 - Nano
• Spring 2004: ECE408 - CSIDC
• Fall 2003: ECE563 - Digital VLSI for Computer Engineers
• Spring 2003: ECE563 - Introduction to VLSI
• Fall 2002: ECE203 - Introduction to Circuits
• Fall 2002: ECE686 - SRC SiGe Contest
• Spring 2002: ECE736 - Advanced VLSI
• Spring 2002: ECE408 - Bluetooth II
• Fall 2001: ECE203 - Circuits
• Fall 2001: ECE563 - VLSI Design
• Spring 2001: EE363 Digital Integrated Circuits
• Spring 2001: EE408 Bluetooth CSIDC Project
• Fall 2000: EE563 Introduction to VLSI
• Spring 2000: EE436 Advanced Digital Design
• Fall 1999: EE563 Introduction to VLSI Design
• Fall 1999: EE736 Advanced VLSI Design
• Spring 1999: EE436 Advanced Digital Design
• Fall 1998: EE563 Introduction to VLSI Design
• Spring 1998: EE436 Advanced Digital Design
• Fall 1997: EE563 Introduction to VLSI Design
• Spring 1997: EE763 Advanced VLSI
• Fall 1996: EE563 Introduction to VLSI Design

Course Development

• ECE 686 - SOC Design
• ECE 436 - Advanced Digital Design
• ECE 563 - VLSI Design: A Top-Down Perspective
• ECE 363 - Digital Integrated Circuits