Tutorial for Cadence Build Gates and Cadence Encounter

(based in part by a tutorial developed by James Stine and his students)


The first step is to create a new directory in which we will run the different programs. These programs do not only need the Verilog source code to be executed, actually they also need a few additional files to be run properly. So here is what we want to do:


1. Create a processing folder (build_gates/) in which the Verilog code will be processed.

Open a terminal (you should be located in home/username/), You can use tc shell, you do not have to use this command to make the compiling work operate, but as this shell provides complementation (tab key) and command recall (up arrow key), it is really going to make your life easier.

- Type: tcsh [step 1].

- Create folder called build_gates/ by typing: mkdir build_gates [step2].


2. Copy the files the compilers will need to be run properly in the processing folder.

These files contain the scripts you will need to customize. Here is what we need to do.

- Create folder called encounter/ by typing: mkdir encounter [step3].

- Copy all the files the compilers are going to need to operate by typing:

cp /home/hplp/osu_stdcells/flow/ami05/* ./build_gates [step4].

FYI, here is the list, not all files are necessary but it’s easier to copy all:

-rwxr-xr-x   1 mrs8n    hplp        2335 Oct 13 13:25 compile_bgx.scr*

-rwxr-xr-x   1 mrs8n    hplp        2390 Oct 13 13:25 compile_dc.scr*

-rwxr-xr-x   1 mrs8n    hplp        2921 Oct 13 13:25 encounter.conf*

-rwxr-xr-x   1 mrs8n    hplp         911 Oct 13 13:25 encounter.io*

-rwxr-xr-x   1 mrs8n    hplp        3530 Oct 13 13:25 encounter.tcl*

-rwxr-xr-x   1 mrs8n    hplp         596 Oct 13 13:25 gds2_encounter.map*

-rwxr-xr-x   1 mrs8n    hplp        1595 Oct 13 13:25 gds2_icfb.map*

-rwxr-xr-x   1 mrs8n    hplp         507 Oct 13 13:25 gds2_seultra.map*

-rwxr-xr-x   1 mrs8n    hplp       23882 Oct 13 13:25 iit05_stdcells.v*

-rwxr-xr-x   1 mrs8n    hplp      103485 Oct 13 13:25 iit05_stdcells.vhdl*

-rwxr-xr-x   1 mrs8n    hplp         798 Oct 13 13:25 pathmill.conf*

-rwxr-xr-x   1 mrs8n    hplp         267 Oct 13 13:25 powrmill.conf*

-rwxr-xr-x   1 mrs8n    hplp        1175 Oct 13 13:25 primetime.scr*

-rwxr-xr-x   1 mrs8n    hplp        3003 Oct 13 13:25 seultra.scr*

Next you need to edit the Build Gates compile script compile_bgx.scr. Use your favorite text editor for this task (here emacs)

Let's open the compile script file first:

Make sure you are in the build_gates/ directory:

cd /home/[username]/build_gates [step5].

Open the compile_bgx.scr file : emacs compile_bgx.scr [step6].

Then you need to modify following lines of the compile script :

Line 11 should look: set my_verilog_files   {controller.v}

Line 14 should look: set my_toplevel_module   controller

Line 21 should look: set my_clock_freq_MHz   100

Line 33: read_tlf  /home/hplp/osu_stdcells/lib/ami05/lib/osu05_stdcells.tlf

Line 65: write_sdc –dc $my_toplevel_module.sdc.temp

Save the modified file and exit the text editor.

We use Cadence Build Gates to synthesize a verilog description to standard cells. The result will be a VHDL file (extension .vh), however you will see that it only instantiates standard cells. This means that Build Gates expresses the functionality of your design by means of only standard cells.
Once compile_bgx.scr is customized as above you just need to execute Build Gates such that it reads all input from the compile script:

Please type: . cadasic [step7].

and then pks_shell -f compile_bgx.scr [step8].

Now you need to copy files controller.vh and controller.sdc from the build_gates/ folder into the encounter/ folder. [step9].


You, also need to download the files encounter.conf and gds2_encounter.map from the class web page into the encounter/ folder. [step10].


Go to the encounter/ folder by typing: cd /home/[username]/encounter.

Now modify file encounter.conf:

Line 8 should look: set rda……..  “controller.vh”

Line 9:set rda…….    “controller.sdc”

Line 10: set rda……   “controller”

Line 20: ut     “/home/hplp/osu_stdcells/lib/ami05/lib/osu05_stdcells.tlf”

Line 28: ut         “/home/hplp/osu_stdcells/lib/ami05/lib/osu05_stdcells.stacks.lef”

It is now time to run the program called Encounter for place and route.

Now go to the encounter directory:

cd /home/[username]/encounter [step11].

Then type: . cadence-soc [step12].

and then

encounter [step13].


The GUI will appear as in the following picture. To zoom in, draw a box with the right mouse button. To go back to full view, hit "f".





Floor planning


The first step is to import the design. Encounter uses configuration files to neatly organize the many pieces that make up a design. Do to "Design -> Import", hit "Load..." and load in the file called "encounter.conf". Hit OK and the design as well as the library data is loaded. Next we need to create a floorplan. Do "Floorplan -> Specify Floorplan". Set the Core Utilization to 0.5 and the space between the core and the boundary to 30um on all sides. A utilization of 50% leaves enough room for buffer insertion during optimization. Inside the 30um we will place supply rings.







Hit OK and floor plan will look as follows.




Next we add supply rings. Do "Floorplan -> Power Planning -> Add Rings". Set the top and bottom layer to Metal3 and set the ring width to. Finally, make the ring centered in the channel. This will create 2 rings, for VDD and GND, around the core.










Finally, now we are ready to route the power grid. Do "Route -> Sroute" and hit OK. The default values are okay. This will route all power tracks in Metal1 and will insert vias between the stripes, rings and tracks. Your layout will look as follows but with no vertical red lines.





To place the cells, do "Place -> Place". Hit OK. The placement should look like this:







Clock Tree Insertion

The first step in timing optimization is to insert a clock tree. First we will have Encounter create a specification file. Do "Clock -> Create Clock Tree Spec" and put "buf" and "inv" as the footprints for the buffer and inverter. Encounter uses footprints to up- and down-size instances of the same functionality.



One could now edit the spec file but we will accept the default.Do "Clock -> Specify Clock Tree" and accept the default file, which is the one we just created.


To create the clock tree do "Clock -> Synthesize Clock Tree" and accept the default values. Next we can run timing optimization based on the clock tree we inserted. Do "Timing -> Optimization" and check "PostCTS". Hit OK and the result can be seen in the command window.




We use "Nanoroute" to perform global and detail routing. It is an extremely powerful router and replaces the older WRoute tool. To route the design, to "Route -> Nanoroute" and hit OK.  To get actual layout on the screen in the gui window hit the layout button in view menu.


Now we can run post-route optimization. This allows Encounter to optimize the design based on actual wires. Any modified net will automatically be re-routed by Nanoroute. To start, do "Timing -> Optimization" and select "postRoute" mode. The result can be seen in the command window. 



The final step is to add filler cells. These are empty cells that provide nwell continuity. Do "Place -> Filler -> Add Filler". Enter "FILL" as the cell name (in the IIT cell library this is the name of the filler cell). The value "FILLER" will be used as the prefix for the instance name of each filler cell added.


After adding filler, hit "f" to redraw the window. It can be seen that the core area is completely covered with cell instances(your layout will be slightly different than following).



    Encounter offers geometry violation check. Do "Verify -> Geometry" and hit OK. The result will be shown in the command line window. If there is a violation, use "Verify -> Violation Browser" to see a list of violations.


    We can also check the connectivity of the design, i.e. missing or in-complete routes or floating pins. Do "Verify -> Connectivity" and hit OK. The result is shown in the command line window.


The last step is to export the design to GDS. This is the format used by Layout Editors (e.g. Cadence Virtuoso) and IC foundries. It requires a map file, to map layer names to layer numbers. In this case we use a map file that matches Mosis layer numbers. Do "Save -> GDS", choose any name for the resulting file and select the map file. Your GDS Structure name should be controller.



Finally, do "Design -> Save Design" to save the entire design to disk. Then next time you run Encounter, you can do "Design -> Restore Design".