Cadence Tutorial 5

The following Cadence CAD tools will be used in this lab: In order to setup your environment to run Cadence applications type (no typo, please do both for now!):

. cdscdk2003
. cdscdk

Please now go to your Tutorial directory and start icfb:

cd Tutorial
icfb &

Let's start our fifth tutorial now!


In this Tutorial 5 we are going to create a layout for our inverter schematic. This time, since we are also doing a layout, we have to worry about design rules and technology. The technology is the same as for the project: the AMI 0.5u C5N CMOS technology with 3 layers of metal, 2 layers of poly, 5 Volt operation and 0.5 micron minimum feature size. More details about the technology are at: For layout we are going to use the SCMOS_SUBM scalable CMOS design rules for submicron processes available from MOSIS. Please revisit your class notes and the MOSIS web page for more details about the SCMOS design rules. The AMI C5N process uses LAMBDA = 0.3u which seems to be in contradiction with the claim that it is a 0.5u process. As explained in class LAMBDA = 0.3u is really chosen for satisfying the design rules for everything else except the transistor length. For the transistor length an extra step is done at MOSIS to reduce it from the drawn 0.6u to 0.5u. Please come and see me if you have questions about this.

There are several consequences of using the LAMBDA-based rules:

Check your schematic of your existing inverter and make sure that their sizes are expressed both in microns and in grid units (half-LAMBDA). The length for example should be 0.6u or 4 grid units. Change the width of the nmos to 5 lambda (10 units) and of the pmos to 10 lambda (20 units). The final schematic should look like this:


Check and save and make sure you don't have any errors or warnings. If everything looks fine it is finally time to start layout.


Since mistakes are common it is a good idea to go now to Options -> User Preferences and increase the Undo level to 10:


Now, whenever you make mistakes you can simply go back with Undo.

First create a layout view of the inverter cell, go to File -> New -> Cell view and fill in inverter for Cell Name, layout for View Name and Virtuoso for Tool.


Two windows should pop-up, the Virtuoso layout window screen and the LSW which is used for choosing the layers to be used:


Now get acquainted to the Virtuoso layout screen. It is quite similar to the Composer window, an important addition are the X and Y absolute coordinates and dX and dY relative coordinates on the top, these are very useful for drawing precise dimensions. The numbers are in microns but notice as you move the cursor that the numbers only change as multiples of 0.15u which is the half-LAMBDA value and also the grid spacing. The configuration forces a "snap to grid" policy which is very good for enforcing the SCMOS design rules. All the custom layout is done by drawing rectangles or paths by doing Create -> Rectangle or Create -> Path and chosing the right layer from the LSW window.

Doing a good layout is more than just drawing rectangles though... The most important aspect is planning: you NEED to use a pencil and paper and make a simple sketch of the layout before you start. You need to decide:

Let's plan our layout! We will use a layout that has a similar topology to the schematic. It will have horizontal vdd (top) and gnd (bottom) lines IN on the left and OUT on the right, all in metal 1. All metal 1 lines will be minimum size (3 lambda, or 6 lambda/2 units, 0.9u) except for vdd and gnd which will be 6 lambda wide (12 lambda/2 units). The two transistors will be arranged horizontally. The layout will be made as compact as possible (i.e. use minimum distances as allowed by DRC wherever possible). With these constraints let's start layout!

First let's do the nmos. We know that the nmos is 5 lambda wide (10 units) which gives us one dimension of the active region. The other dimension can be obtained by adding together all the features that are needed and their minimum sizes according to the design rules: we need the gate (length 2 lambda), two contacts of active to metal1 (2 lambda each), two minimum distances between contact and poly (2 lambda each) and two minimum overlap of active over contact (1.5 lambda each). If we add all of these together we get a total of 13 lambda. This means that our active region for the nmos is 5x13 lambda. Let's draw a rectangle 5x13 lambda (1.5x3.9 microns) of nactive (same as active but easier for humans to read) starting from the 0.00,-1.80 point down and to the right. First click on nactive in the LSW window, then do Create -> Rectangle and first click when the absolute coordinates are X: 0.00, Y: -1.80, then move until the relative coordinates show dX: 3.90, dY: -1.50. Now do Window -> Fit All followed by Window -> Zoom -> Out by 2.


Now let's draw the gate. We'll draw another rectangle, 2 lambda wide, in the middle of the active region so that it overlaps the area by two lambda on each side. Click on poly in the LSW and then start from the point X: 1.65, Y: -3.90 to X: 2.25, Y: -1.20


Now we need to add the two contacts, both 2 lambda on each side (0.60) and 2 lambda from poly and 1.5 lambda from the outside. Click on cc in the LSW and then draw the first rectangle from X: 0.45, Y: -2.85 to X: 1.05, Y: -2.25, then copy the rectangle to the position of the other contact by doing Edit -> Copy.


With this the active area for the nmos is done but we still need to put nselect around the active. Before we do that let's define the substrate contact area. Let's draw a pactive rectangle that is 5 lambda on each side adjacent to the nmos transistor, then copy a contact into the middle of this region.


Now we need to surround the active area with select rectangles, nselect for the transistor and pselect for the substrate contact. These areas need to be 2 lambda larger than the active. Click on nselect first and draw a rectangle from X: 0.00 Y: -1.20 to X: 4.50 Y: -3.90


Then draw a pselect rectangle around the substrate contact.


IMPORTANT: In general I suggest you don't look too much at the actual coordinates, many times you can use your eyes and the fact that the cursor snaps to grid to assure correct sizes. For example in the case of the select we know that it needs to be 2 lambda over the active, the same distance as the poly overlap. This can help you to draw the correct sizes without looking at the coordinates.

With this the nmos is complete, we can do the pmos. The pmos is drawn in the same fashion except that nactive becomes pactive and viceversa and nselect becomes pselect and viceversa. Also the width is twice larger and we need two contacts on each side. Notice that we have drawn the nmos with the active area 6 lambda below the Y: 0.00 axis, draw the pmos 6 lambda above the Y: 0.00 axis. You can use copy, stretch instead of drawing some of the shapes to make the layout faster. In the end you should get something like this:


There is just one more element needed for the transistors: the nwell for the pmos. Draw a rectangle that surrounds the pmos active area by 6 lambda (1.8 microns), you should get:


We also need to add metal 1 above the contacts that needs to overlap the contacts by 1 lambda.


It is now time to save your design (Design -> Save) and run a preliminary DRC. Go to Verify -> DRC...


then click on OK. Check your CIW window, you should have no errors, in case you have errors you need to go back and fix them.

We are still not done with this lab yet! Until now we did what is usually called placement, we still need to route our schematic. First let's route the output, click on metal 1 and then Create -> Path and draw a path from the drain of the pmos to the drain od the nmos (right side). The path is only 3 lambda wide so draw it aligned to the right most side. You have to double click to end the path.


Now draw another path centered around the 0 axis to the end of the nwell.


Now let's connect the input. Draw a poly path between the two gates. Observe that the default width of the poly line is correct: 2 lambda.


Now start another poly line centered around the 0 axis going to the left and after you pass the 0,0 point and change to metal 1 by using the Change to Layer in the Create Path window. This should automatically insert a contact between poly and metal 1, click once to place the contact structure adjacent to the 0,0 point to the right. Double click when you reach the left-most edge of the nwell to end the path. In order to see all the layers in the contact "pcell" type Shift-F with the cursor in the layout window.


The only items left now are the vdd and gnd connections, we are going to use Create -> Polygon for those (we could also use rectangles or paths). Create the polygon using the points:

X: -1.35 Y: 4.65
X: -1.35 Y: 5.55
X: -3.30 Y: 5.55
X: -3.30 Y: 7.35
X: 5.70 Y: 7.35
X: 5.70 Y: 5.55
X: 1.35 Y: 5.55
X: 1.35 Y: 4.65
Again observe that except for a few of the points you don't really need to look for the actual coordinates since they align with existing structures (e.g. well or metal 1). The only sizes that you have to worry about are the distance to other metal 1 (e.g. drain) which needs to be >3 lambda and width of the line which we decided to be 6 lambda.


For the ground we will simply copy this polygon, go to Edit -> Copy and then click on Upside Down in the Copy window.


Now place the copied polygon at the bottom making conatct with the nmos source.


Save and run another DRC and make sure you have no errors. Congratulations, this is the end of Tutorial 5.