VHDL/Verilog Simulation Tutorial

The following Cadence CAD tools will be used in this tutorial:

Computer Account Setup

Please revisit Unix Tutorial before doing this new tutorial.

If you use Exceed from a PC you need to take care of this extra issue. The Cadence software has an annoying screen/refresh problem when run on a PC via Exceed. You need to do the following in order to solve the problem:
Under Xconfig -> Performance.

  1. Enable Save Unders
  2. Enable Change Maximum Backing Store to Always
  3. Alter Default Backing Store to When Mapped
  4. Alter Minimum Backing Store to When Mapped
You have to exit Exceed for the changes to take effect.


In order to setup your environment to run Cadence applications you need to open an xterm window and type (EVERY TIME you login and in each window you want to run a Cadence tool)

. cadence2009

this script modifies your environment (sets PATH and exports variables). To see your current environment type the following at the prompt:


Running the Cadence Simulation tools

Now you should be able to run the Cadence tools. Never run Cadence from your root directory, it creates many extra files that will clutter your root. Instead please create a directory (e.g. cadence) and another directory for the design (e.g. tutorial) and finally one for the HDL files (e.g. HDL) by typing:

mkdir cadence
cd cadence
mkdir tutorial
cd tutorial
mkdir HDL

For this tutorial you will need a few extra files, please download the following files in the HDL directory:


From the tutorial directory type:

nclaunch &

The command nclaunch & starts NCSim in the background and you should get the NCLaunch startup window:


Please click on Multiple Step and you should now get the main NCLauch window:


The window has four areas:

Please try to familiarize yourself with the main window, click on the menus, etc. For more information on the various Cadence tools I encourage you to read the corresponding user manuals. You can get to the manuals by pressing Help -> NCLaunch User Guide on the right of the Menu Bar. A Web Browser should pop-up. There are also tutorials available Help -> Tutorials. Spend some time browsing the manuals to understand what is available (a lot!). During the semester you will have to look for information in the on-line manuals to complement the (limited) info given by these tutorials. Actually you can think of this tutorial as a subset of the one available under help!

Now we need to set the work directory and create a work library (to contain your circuits) so go to File -> Set Design Directory from the File menu of the Menu Bar. First set the design directory to the tutorial directory that you just created (this should be automatic if you started NCLaunch from the tutorial directory as described here):


then click on Create cds.lib File and click Save (you should only need to do this once when you run the tool for the first time)


and finally click OK to Include default libraries


Finally, making sure that worklib has appeared for Work Library click OK on the Set Design Directory pop-up window. Please notice that the Library Browser window (right side) of NCLaunch has become populated now.

There are 3 steps that we need to perform now (remember we chose multistep):

In order to compile you first need to select the various files in the File Browser (left side) by clicking on the mouse left button (simultaneously press on shift for multiple selections), then click on the corresponding buttons in the Menu Bar (in this case the VLOG button) or explicitly go to Tools -> Verilog Compiler.... Now is actually a good time to look at these files as well, you can do that for example by clicking on the file, then going to File -> Edit, you should see the actual file in a text editor:


Close the text editor without modifying the file. Now compile both accu.v and accu_test.v in that order.

Caution! The order of compilation is important in case there are dependencies among the files. In the case the testbench is the "top" file and needs to be compiled last!

Make sure there are no errors in the Console Window (always keep an eye on that window for errors and warnings).

In order to elaborate first click on the + in front of the worklib on the Library Browser window in order to see it's contents:


Now select the top file under worklib (stimulus) then click on the Elaborate button in the Menu (immediately to the right of the VLOG button), or go to Tools -> Elaborator....

Finally we can simulate! Click on the + sign in front of the Snapshots library to expand its contents, then select worklib.stimulus:module and click on Simulate (next to the right of elaborate) or go to Tools -> Simulator.... This should launch the Simvision Design Browser and Console windows:


Click on stimulus on the left window, then on the Waveform button (the one that looks like a set of white digital waveforms on a black background, sixth from the right), this should open a new Waveform window. Now press on the Run button on the Design Browser window (first on the left, looks like a Play button on a CD player). This should now display the signal waveforms that validate correct functionality for the accumulator (increment by one for every clock cycle):


Congratulations, this is the end of the Simulation Tutorial.