STT-RAMs show the promise to be the universal memory device with applications in embedded devices. There are outstanding challenges that need to be addressed before a wide-scale adoption of this technology happens. The solution to these challenges lie in integration of emerging high performance spintronic materials as well as clever circuit based techniques to operate these devices at their peak performance. In this work we present a material-device-circuit co-design framework that connects the properties of materials and transport physics to circuits and systems performance. To illustrate the use of this framework we study present and next generation STT-RAM technology in terms of energy-delay-reliability performance metrics and suggest possible directions for future generation devices.