Analog Turbo Decoder (SRC Design Challenge)
As part of the SRC Design
Challenge, members of the HPLP Laboratory have designed an Analog Turbo
Decoder in order the show the performance gains of turbo decoding using
a SiGe BiCMOS process. The design makes use of translinear
networks used to multiply arrays of currents for the purpose of
performing the decoding algorithm in an analog architecture.
Team Members:
Layout of our chip:
Last Updated:
Jan. 15, 2004
Email:
hplp@virginia.edu
