Nanoelectronic Circuit Design



The specific research efforts of the HPLP group, in conjunction with the NIRT group at the University of Virginia, in the area of nanoelectronics has to do with developing accurate yet robust device models that can be used for circuit design and to apply these models in the design of realizable nanoelectronic circuits.  As a result of this work, a Universal Device Model (UDM) has been developed which can be fit to any set of current vs. voltage data, whether experimental or theoretical, to produce an equation representing a specific device.

Using the UDM for circuit simulations, we have worked on various circuit designs which seem promising for use in molecular electronic architectures.  Among the types of circuits explored are cross bar designs and logic circuits consisting of molecular devices which behave like tunnel diodes.

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People:

        Mircea R. Stan
        Garrett Rose
        Matthew Ziegler
        Steve Driskill

Publications:

        M. M. Ziegler, G. S. Rose, and M. R. Stan, “A Universal
             Device Model for Nanoelectronic Circuit Simulation,” in
             Proceedings of the 2002 2nd IEEE Conference on
             Nanotechnology, August 2002, pp. 83–88.
        M. M. Ziegler and M. R. Stan, “Design and Analysis of
             Crossbar Circuits for Molecular Nanoelectronics,” in
             Proceedings of the 2002 2nd IEEE Conference on
             Nanotechnology, August 2002.
        M. M. Ziegler and M. R. Stan, “A Case for CMOS/Nano
             Co-Design,” in International Conference on Computer Aided
             Design, November 2002.
        M. M. Ziegler and M. R. Stan, “The CMOS/nano Interface from
             a Circuits Perspective,” The International Symposium on
             Circuits and Systems (ISCAS), Bangkok, Thailand, May 2003.
        G. S. Rose and M. R. Stan, “Memory Arrays Based on
             Molecular RTD Devices,” to be presented at the 2003 3rd
             IEEE Conference on Nanotechnology, San Francisco, CA,
             August 2003.

Related Links of Interest:

        Purdue NanoHub
        Reed Lab at Yale
        Seminario Research Group
        TranSIESTA
        MITRE Nanoelectronics
        NSF
        UVA FEST

Acknowledgements:
This work was supported in part by a University of Virginia FEST grant and by an NSF NIRT award.

Last Updated: Jan. 21, 2004
Email: hplp@virginia.edu

High-Performance Low-Power (HPLP) VLSI Laboratory